Embodiments of the present invention relate to a test apparatus for testing a device under test. Further embodiments of the present invention relate to a method for testing a device under test. Further embodiments of the present invention relate to a tester for testing a device under test. Other embodiments relate to a method for testing a device under test and to a computer program.
To minimize power consumption, RF power amplifiers are operated at marginal supply voltage levels. This drives them into compression, leading to strong inter-modulation products. Digital predistortion (DPD) of the baseband I/O inputs mitigates this effect. For further power reduction, supply voltages may dynamically track the RF envelope, also known as envelope tracking (ET). Digital predistortion is usually performed as part of a straightforward test consisting of two test steps. In a first step, the device's non-linearity is computed from its response to a fixed test waveform. In a second step, an individually predistorted waveform is computed, downloaded and applied to each device being tested in order to measure the remaining non-linearity after predistortion. This second step causes a significant test time penalty, especially in multi-site test, since downloads must be executed serially with respect to the tested devices. This test time penalty results in a high time effort when testing and judging a device under test.
In addition, DUTs of a production series, a production lot or of the same type may comprise deviations between single DUTs, such as production or material tolerances, errors or failures. Therefore DUTs may show deviant behavior, i.e., deviant signal response to identical signal input. Also qualitative parasitic effects like dirt, e.g., on printed circuit boards of a DUT, may lead to deviations of the behavior.
Hence, for example, there is a need for a reduction of the test time of such tests. A reduced test time would help to increase testing capacities of a tester testing the devices under test and therefore lead to a higher throughput of a tester testing the devices under test.